Thin titanium nitride layers used in conjunction with tungsten

ABSTRACT

Titanium nitride layers a less than 30 nm thickness are formed by physical vapor deposition and used as barrier layers for tungsten deposition. The titanium nitride layers are annealed in the presence of nitrogen or a nitrogen compound.

BACKGROUND

[0001] The present invention relates to physical vapor deposition oftitanium nitride.

[0002] Titanium nitride has been used as a barrier and adhesion layer infabrication of tungsten plugs in semiconductor integrated circuits.Tungsten plugs interconnect different conductive layers separated by adielectric. Frequently used dielectrics are silicon dioxide and siliconnitride. Tungsten does not adhere well to silicon dioxide and siliconnitride, so titanium nitride has been used to promote adhesion. Inaddition, titanium nitride serves as a barrier layer preventing achemical reaction between WF₆ (a compound from which the tungsten isdeposited in a chemical vapor deposition process) and other materialspresent during tungsten deposition. See “Handbook of SemiconductorManufacturing Technology” (2000), edited by Y. Nichi et al., pages344-345.

[0003]FIGS. 1, 2 illustrate a typical fabrication process. A dielectriclayer 110 is deposited over a layer 120 which can be a metal or siliconlayer. A via 130 is etched in the dielectric. A thin titanium layer 140is deposited over dielectric 110 and into the via 130 to improve contactresistance (the titanium dissolves the native oxide on layer 120). Thentitanium nitride layer 150 is deposited. Then tungsten 160 is depositedby chemical vapor deposition (CVD) from tungsten hexafluoride (WF₆).Tungsten 160 fills the via. Layers 160, 150, 140 are removed from thetop surface of dielectric 110 (by chemical mechanical polishing or someother process). See FIG. 2. The via remains filled, so the top surfaceof the structure is planar. Then a metal layer 210 is deposited. Thelayers 160, 150, 140 in via 130 provide an electrical contact betweenthe layers 210 and 120.

[0004] Titanium nitride 150 can be deposited by a number of techniques,including sputtering and chemical vapor deposition (CVD). Sputtering isless complex and costly (see “Handbook of Semiconductor ManufacturingTechnology”, cited above, page 411), but the titanium nitride layersdeposited by sputtering have a more pronounced columnar grain structure.FIG. 3 illustrates columnar monocrystalline grains 150G in titaniumnitride layer 150. During deposition of tungsten 160, the WF₆ moleculescan diffuse between the TiN grains and react with titanium 140. Thisreaction produces titanium fluoride TiF₃. TiF₃ expands and causesfailure of the TiN layer. The cracked TiN leads to a higher exposure ofTiF₃ to WF₆, which in turn leads to the formation of volatile TiF₄. TiF₄causes voids in the W film which are known as “volcanoes”. To avoid thevolcanoes, the sputtered titanium nitride layers have been made as thickas 40 nm, and at any rate no thinner than 30 nm. In addition, thesputtered titanium nitride layers have been annealed in nitrogenatmosphere to increase the size of the TiN grains.

SUMMARY

[0005] The inventor has discovered that under some conditions thinnerannealed layers of sputtered titanium nitride unexpectedly providebetter protection against the volcanoes than thicker layers. In someembodiments, fewer volcanoes have been observed with a TiN layerthickness of 20 nm than with 30 nm. In fact, no volcanoes have beenobserved in some structures formed with the 20 nm TiN layers. Why thethinner TiN layers provide better protection is not clear. Withoutlimiting the invention to any particular theory, it is suggested thatperhaps one reason is a lower stress in the thinner annealed layers anda higher density of the TiN grains.

[0006] The invention is applicable to physical vapor depositiontechniques other than sputtering. Additional features and embodiments ofthe invention are described below.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIGS. 1-3 are cross sectional views of prior art semiconductorstructures in the process of fabrication.

[0008] FIGS. 4-6 are cross sectional and perspective views ofsemiconductor structures in the process of fabrication according to oneembodiment of the present invention.

DESCRIPTION OF PREFERRED EMBODIMENTS

[0009]FIG. 4 is a cross sectional and perspective view of a dualdamascene semiconductor structure in the process of fabricationaccording to one embodiment of the present invention. Layer 120 ispolysilicon formed by chemical vapor deposition (CVD) over amonocrystalline silicon wafer 410. Before fabrication of layer 120, thewafer 410 may have been processed to form devices such as MOS transistor420. The transistor's source/drain regions 430 were formed in substrate410, gate insulation 440 was formed over the substrate, and gate 450 wasformed over the gate insulation. Other devices, including non-MOSdevices, could be formed using known techniques. Layer 120 can also bepart of substrate 410 (this embodiment is not shown in FIG. 4).

[0010] In the embodiment of FIG. 4, dielectric 460 was deposited overthe wafer. Then layer 120 was formed as described above, and waspatterned by a plasma etch. An exemplary thickness of layer 120 is 150nm.

[0011] Dielectric layer 110 was deposited over the layer 120. In someembodiments, dielectric 110 was a combination of two silicon dioxidelayers. The first layer was PSG (phosphosilicate glass) deposited bychemical vapor deposition (CVD). The second layer was silicon dioxidedeposited by CVD from TEOS. The combined thickness of the two layers wasapproximately 900 nm.

[0012] Then a photoresist layer (not shown) was deposited and patternedphotolithographically to define a via 464. In some embodiments, the maskopening defining the via was round in top view, with a diameter of 0.18μm. The via was formed in layer 110 with a plasma etch.

[0013] The photoresist was removed, and another layer of photoresist(not shown) was deposited and patterned photolithographically to definea trench 470 in dielectric 110 for a tungsten interconnect. In someembodiments, the trench length was approximately 1 mm. The trench widthwas 0.22 μm. The trench was etched with a timed etch to a depth ofapproximately 250 nm. Via 464 was fully exposed at the bottom of thetrench.

[0014] Then the top surface of the structure was exposed to RF plasma inargon atmosphere for 10 seconds. The argon flow was 5 sccm (standardcubic centimeters per minute). The RF power was 315 W. This operationremoved native oxide from layer 120. Also, this operation smoothened(rounded) top edges 480 of trench 470 and via 464. The rounded edges aredesirable to reduce stress in titanium nitride 150 (FIG. 5) at theseedges so as to reduce the risk of volcano formation. The RF plasmaoperation was performed in a system of type ENDURA available fromApplied Materials of Santa Clara, Calif.

[0015] Then titanium layer 140 (FIG. 5) was sputter deposited from atitanium target. The sputtering was performed at a temperature of 200°C. in argon atmosphere. The base pressure (the pressure before the argonflow was turned on) was 5×10⁻⁷ torr. The DC power was 4000 W, the RFpower was 2500 W. The wafer AC bias was 150 W. The titanium depositionwas performed in a system of type ENDURA, in an ionized metal plasma(IMP) chamber of type Vectra, available from Applied Materials.

[0016] The thickness of Ti layer 140 was varied. In one embodiment, thethickness was 10 nm. In another embodiment, the thickness was 36 nm.

[0017] Then titanium nitride 150 was deposited by reactive sputteringfrom a titanium target in a nitrogen atmosphere. The base pressure (thepressure before the nitrogen flow was turned on) was 5×10⁻⁷ torr. Thenitrogen flow was 28 sccm (standard cubic centimeters per minute), theDC power was 4000 W, the RF power was 2500 W, the wafer bias was 150 W.The deposition temperature was 200° C. The deposition was performed in asystem of type ENDURA, in an IMP chamber of type Vectra, available fromApplied Materials.

[0018] The thickness of the TiN layer 150 was 20 nm in one embodiment,30 nm in another embodiment.

[0019] Then the structure was heated to a temperature between 600° C.and 700° C. for 20 to 30 seconds in a nitrogen atmosphere. (Thisoperation is referred to herein as Rapid Thermal Anneal, or RTA.) Thebase pressure was 100-120 torr, the nitrogen flow was 8 slm (standardliters per minute). The temperature was 620° C. in one embodiment, 670°C. in another embodiment. The anneal was performed in a system of typeHEATPULSE 8800 available from AG Associates, Inc., of San Jose, Calif.The anneal is believed to have increased the lateral size of TiN grains150G (FIG. 3).

[0020] Then tungsten layer 160 was deposited by CVD in two stages. Atthe first stage, the chemical reaction was:

2WF₆+3SiH₄→2W+3SiF₄+6H₂

[0021] This stage lasted 10 seconds. Then the silane (SiH₄) flow wasturned off, and the hydrogen flow was turned on for the second stage.The chemical reaction was:

WF₆(vapor)+3H₂(vapor)→W (solid)+6HF (vapor).

[0022] See S. Wolf, “Silicon Processing for the VLSI Era”, vol. 2(1990),page 246, incorporated herein by reference. Both stages were performedin a system of type CONCEPT 1 available from Novellus Systems of SanJose, Calif. The silane flow was 20 sccm. The hydrogen flow was 12-15slm (standard liters per minute). The WF₆ flow was 350 sccm. Thepressure was 40 torr. The temperature was 400° C.

[0023] Then the layers 160, 150, 140 were polished off the top ofdielectric 110.2 by CMP. The resulting structure is shown in FIG. 6.Prior to CMP, the structure was examined for volcanoes using an opticalmicroscope and SEM and STEM microscopes. The results are given in Table1 below. The second column of Table 1 indicates the temperature of theRapid Thermal Anneal, described above, performed after the deposition ofTiN 150 before the deposition of tungsten 160. In Embodiment No. 1, theanneal was omitted. TABLE 1 Ti/TiN thickness: Ti/TiN thickness:Embodiment RTA of 10 nm/20 nm 36 nm/30 nm No. TiN Volcanoes observed?Volcanoes observed? 1. None Yes Yes 2. 620° C. No Yes, but fewer than inEmbodiment No. 1 3. 670° C. No No

[0024] These results show, unexpectedly, that the use of thinner Ti andTiN layers in combination with the RTA can provide a better protectionagainst the volcanoes than thicker layers without the RTA. The thinnerlayers can eliminate the volcanoes at the lower RTA temperature of 620°C. Lower RTA temperatures are desirable to reduce impurity diffusionduring the RTA, to prevent melting or softening of materials having lowmelting temperatures (e.g. aluminum), and reduce wafer warping.

[0025] The invention is not limited to the particular materials,dimensions, structures, or fabrication processes described above. Theinvention is not limited to a thickness or composition of any particularlayer, or the number, shape and size of vias 464 or trenches 470. Thetrench length, for example, is 2 μm in some embodiments, and otherlengths are possible. The invention is not limited to the particular gasflow rates, temperatures, or any other fabrication parameters orequipment. Some embodiments use nitrogen sources other than purenitrogen for the RTA or titanium nitride deposition. For example,ammonia (NH₃) or H₂/N₂ can be used. The invention is not limited to theRapid Thermal Anneal or to any particular anneal temperature. Non-rapidanneals can be used. The anneal can be performed with plasma or withother heating techniques, known or to be invented. The invention isapplicable to TiN sputtered from a TiN target. The invention isapplicable to single damascene, dual damascene, and other structures,for example, to tungsten plugs formed in contact vias in non-damascenestructures, and to tungsten features other than plugs. Titanium 140 isomitted in some embodiments. The invention is applicable to differenttungsten CVD techniques, including tungsten deposition from WCl₆ ratherthan WF₆. The invention is not limited by particular materials chosenfor the layers 120, 110, 460. Some embodiments involve non-siliconsemiconductor materials. The invention is not limited to any particularsputtering process, and further is applicable to TiN deposited byphysical vapor deposition techniques other than sputtering. For example,pulsed laser deposition and other evaporation techniques can be used.See “Handbook of Semiconductor Manufacturing Technology” (2000), citedabove, pages 395-413, incorporated herein by reference. Layer 120 (FIG.4) can be a metal layer, and can be part of the second, third, or highermetallization layers. The term “layer”, as used herein, may refer to acombination of two or more other layers. The invention is defined by theappended claims.

1. A fabrication method comprising: forming a titanium nitride layer over a substrate by physical vapor deposition, the titanium nitride layer being less than 30 nm thick; heating the titanium nitride layer while exposing the titanium nitride layer to nitrogen and/or a nitrogen compound; and then forming a tungsten layer over and in physical contact with the titanium nitride layer by chemical vapor deposition.
 2. The method of claim 1 wherein the titanium nitride layer is formed by sputtering.
 3. The method of claim 2 wherein the titanium nitride layer is less than 25 nm thick.
 4. The method of claim 2 wherein the titanium nitride layer is less than 22 nm thick.
 5. The method of claim 2 wherein the titanium nitride layer is about 20 nm thick.
 6. The method of claim 1 further comprising forming a titanium layer before the titanium nitride layer, the titanium nitride layer being in physical contact with the titanium layer.
 7. The method of claim 6 wherein the titanium layer is less than 36 nm thick.
 8. The method of claim 6 wherein the titanium layer is about 10 nm thick.
 9. The method of claim 1 wherein heating the titanium nitride layer comprises exposing the titanium nitride layer to the nitrogen and/or the nitrogen compound at a temperature above 600° C.
 10. The method of claim 1 wherein heating the titanium nitride layer comprises exposing the titanium nitride layer to the nitrogen and/or the nitrogen compound at a temperature of about 670° C. for 20-40 seconds.
 11. The method of claim 1 wherein heating the titanium nitride layer comprises exposing the titanium nitride layer to the nitrogen and/or the nitrogen compound at a temperature of about 620° C. for 20-40 seconds.
 12. The method of claim 1 wherein the substrate is a semiconductor substrate.
 13. The method of claim 12 further comprising: forming a circuit element in or over the substrate; forming an insulating layer over the substrate and the circuit element; forming an opening in the insulating layer, the opening exposing the circuit element, the opening comprising a trench at least 2 μm long; wherein the titanium nitride layer and the tungsten layer are present in the opening and the tungsten layer electrically contacts the circuit element through the titanium nitride layer in the opening.
 14. The method of claim 13 wherein the trench is at least 1 mm long.
 15. The method of claim 14 further comprising depositing a titanium layer over the insulating layer before depositing the titanium nitride layer, wherein the tungsten in the opening electrically contacts the circuit element through the titanium and titanium nitride layers.
 16. The method of claim 15 wherein the trench does not penetrate the insulating layer but a via at the bottom of the trench penetrates the insulating layer and exposes the circuit element, wherein the titanium layer physically contacts the circuit element at the bottom of the via.
 17. The method of claim 14 wherein the circuit element is conductive.
 18. The method of claim 14 wherein the circuit element comprises a metal or semiconductor material.
 19. The method of claim 14 further comprising rounding top edges of the trench.
 20. The method of claim 14 wherein the opening comprises a via at a bottom of the trench, and the method further comprises rounding top edges of the trench and the via.
 21. A method for fabricating an integrated circuit, the method comprising: forming a circuit element in or over a semiconductor substrate; forming an insulating layer over the circuit element; forming an opening in the insulating layer to expose the circuit element at a bottom of the opening; forming a titanium layer over the insulating layer, the titanium layer overlaying sidewalls of the opening, the titanium layer being less than 15 nm thick; forming a titanium nitride layer over the titanium layer, the titanium nitride layer being less than 25 nm thick, the titanium nitride layer being formed by sputtering; heating the titanium nitride layer while exposing the titanium nitride layer to nitrogen and/or a nitrogen compound; forming a tungsten layer by chemical vapor deposition over the titanium nitride layer, the tungsten layer at least partially filling the opening and electrically contacting the circuit element through the titanium and titanium nitride layers.
 22. The method of claim 21 wherein the opening comprises a trench at least 2 μm long.
 23. The method of claim 21 wherein the opening comprises a trench at least 1 mm long.
 24. The method of claim 21 wherein heating the titanium nitride layer comprises heating the titanium nitride layer in an ambient temperature of about 670° C. for 20-40 seconds.
 25. The method of claim 21 wherein heating the titanium nitride layer comprises heating the titanium nitride layer in an ambient temperature of about 620° C. for 20-40 seconds.
 26. A structure formed by the method of claim
 1. 27. A structure formed by the method of claim
 21. 28. A structure comprising: a substrate; a titanium nitride layer formed over the substrate and having substantially a columnar grain structure, the titanium nitride layer being less than 30 nm thick; a tungsten layer overlying and physically contacting the titanium nitride layer.
 29. The structure of claim 28 further comprising a titanium layer overlying the substrate and physically contacting the titanium nitride layer.
 30. The structure of claim 29 wherein the structure is a semiconductor integrated circuit.
 31. The structure of claim 30 further comprising: a circuit element formed in or over the substrate; an insulating layer overlying the circuit element and having an opening over the circuit element; wherein the tungsten layer electrically contacts the circuit element through the opening through the titanium nitride and titanium layers.
 32. The structure of claim 31 wherein the titanium nitride layer is less than 22 nm thick, and the titanium layer is less than 12 nm thick.
 33. The structure of claim 30 wherein the opening comprises a trench having a lateral dimension of at least 2 μm.
 34. The structure of claim 30 wherein the opening comprises a trench having a lateral dimension of at least 1 mm. 